1. Technical Field
This disclosure relates to semiconductor memories and more particularly, to a trench capacitor semiconductor memory with retrograded doping along a trench sidewall to prevent parasitic leakage.
2. Description of the Related Art
Integrated circuits (ICs) employ capacitors for charge storage purposes. For example, memory devices, including random access memories (RAMS) such as dynamic RAMs (DRAMs) store a charge in a capacitor. The level of charge ("0" or "1") in the capacitor represents a bit of data.
A DRAM IC includes an array of memory cells interconnected by rows and columns. Typically, the row and column connections are referred to as wordlines and bitlines, respectively. Reading data from or writing data to the memory cells is accomplished by activating the appropriate wordlines and bitlines.
Typically, a DRAM memory cell comprises a metal oxide semiconductor field effect transistor (MOSFET) connected to a capacitor. The transistor includes a gate and first and second diffusion regions. The first and second diffusion regions are referred to either as the drain and the source, respectively, depending on the operation of the transistor. For convenience, the terms drain and source are interchangeable. The gate of the transistor is coupled to a wordline, and a first diffusion region is coupled to a bitline. A second diffusion region of the transistor is coupled to the capacitor or storage node. Applying the appropriate voltage to the gate switches on the transistor, forms a conductive path to the capacitor. This conductive path is closed when the transistor is switched off.
A trench capacitor for a memory device is a three-dimensional structure formed into a silicon substrate. A conventional trench capacitor includes a trench etched into the substrate. The trench is typically filled with n+ doped polysilicon which serves as one plate of the capacitor (i.e., storage node). The second plate of the capacitor, referred to as a buried plate, is formed by, for example, outdiffusing n+ dopants from a dopant source into regions of the substrate surrounding the lower portion of the trench. A dielectric layer is provided to separate the two plates forming the capacitor. To prevent or reduce parasitic leakage that occurs along the upper portion of the trench to an acceptable level, an oxide collar of sufficient thickness is provided in the trench. Typically, the oxide is thick enough to reduce the current leakage to less than about 1fA/cell.
Continued demand to shrink devices has facilitated the design of DRAMs with greater density and smaller feature size and cell area. For example, design rules have been scaled down to 0.12 microns and below. At the smaller groundrules, the control of vertical parasitic MOSFET leakage between the storage node diffusion and the buried plate becomes problematic due to the smaller trench dimensions. The smaller trench opening necessitates a corresponding reduction in collar thickness to facilitate filling the trench with storage node material. To reduce the parasitic leakage to below an acceptable level, the thickness of the collar needs to be about 20-90 nm, depending on the operating voltage conditions. Such a thick collar hinders the filling of the smaller diameter trench.
One way to reduce parasitic leakage is to increase dopant concentration of a well on which the transistor for the memory cell is formed. However, raising the dopant concentration of the well increases electric fields in depletion regions, which results in a sharp increase in junction leakage. This is especially true when crystallographic defects are present in the silicon.
Referring to FIG. 1, a conventional trench capacitor cell 100 is shown employing an n-channel MOSFET. The conventional trench capacitor cell 100 is typically part of an array of cells interconnected by wordlines and bitlines on a semiconductor chip.
Cell 100 includes a trench capacitor 160 formed in a substrate 101. The trench is typically filled with polysilicon (poly) to form a storage node 161 that is doped with n-dopants. Buried plate 165 is also doped with n-type dopants and surrounds the lower portion of the trench. In the upper portion of the trench, a collar 168 is formed to reduce parasitic leakage. A node dielectric 163 separates storage node 161 and buried plate 165. A buried well 170 includes n-type dopants and is provided to connect buried plates 165 in the array of cells 100. A p-well 173 is above buried well 170.
A transistor 110 is provided which includes a gate 112, a source 113 and a drain 114 diffusion regions including n-type dopants. The source 113 and drain 114 may be interchanged depending on the operation of transistor 110. Gate 112 represents a wordline for activating transistor 110 (active wordline). Connection of transistor 110 to storage node 161 is achieved through buried strap 125 and diffusion region 114.
A shallow trench isolation (STI) 180 is provided to isolate cell 100 from other cells or devices. A wordline 120 may be formed over the trench, and wordline 120 is isolated from the trench by STI 180. Wordline 120 is referred to as a passing wordline. This configuration is referred to as a folded bitline architecture.
An interlevel dielectric layer 189 is formed over the wordlines. A conductive layer, representing a bitline 190 is formed over interlevel dielectric layer 189. A bitline contact 186 is provided through interlevel dielectric layer 189 to connect diffusion 113 to bitline 190.
As described previously, smaller groundrules which produce smaller trench dimensions require thinner collars. However, thinner collars may be inadequate to prevent excessive parasitic leakage. A vertical parasitic transistor 122 is formed on the sidewall of the trench. Parasitic transistor 122 includes buried strap diffusion 125 and buried plate 165 as its drain and source (respectively). When an appropriate charge is stored within the trench, collar 168 acts as a gate oxide and storage node 161 acts as a gate conductor. A channel is formed in substrate 101 adjacent to the trench and within p-well 173. This vertical parasitic transistor is highly undesirable and results in loss of stored charge from the capacitor.
Therefore, a need exists for a method for reducing parasitic transistors in trench capacitors without increasing the thickness of a dielectric collar formed in the trench.